It’s time someone solidly stated the difference between GDDR and DDR. It’s also important to explain GDDR3 vs GDDR5, which are currently the 2 most common forms of memory found in video cards. Both of these topics are popular to discuss, producing plenty of information and misinformation.
In this article, I will explain how GDDR is NOT simply DDR with a G for graphics on the front of it. Then I will discuss the difference between the latest versions of GDDR, which is relevant in today’s GPU market. Along the way, I will attempt to clarify all the confusing terminology that gets thrown around. These terms include “interface”, “bus”, “channel”, “clock cycle”, “width”, “lines”, and “bandwidth.”
Quick Answers for the Impatient
- GDDR is not the same as DDR. Overall, GDDR is built for much higher bandwidth, thanks to a wider memory bus.
- GDDR has lower power and heat dispersal requirements compared to DDR, allowing for higher performance modules, with simpler cooling systems.
- DDR1, DDR2, and DDR3 have a 64 bit bus (or 128 bit in dual channel). GDDR3, comparatively, commonly uses between a 256 bit bus and 512 bit bus, or interface (across 4-8 channels).
- GDDR3 has a 4 bit prefetch and GDDR5 has an 8 bit prefetch, making GDDR5 twice as fast as GDDR3 in apples to apples comparisons.
- GDDR can request and receive data on the same clock cycle, where DDR cannot.
- DDR1 chips sends 8 data bits for every cycle of the clock, GDDR1 sends 16 data bits.
The History- DDR1 and GDDR1
10 Years ago the first double data rate (DDR) RAM was commercially produced in 266 MHz modules. It ran with a 64 bit “memory bus”, just like traditional PC100/PC133 SDRAM, but had double the bandwidth at 2.1 GB/sec. It still operated with a 133 MHz clock, but achieved an effective clock rate of 266MHz by using both the leading and trailing edge of the clock cycle.
This concept of using both sides of the clock cycle actually existed in graphics memory before system memory. It wasn’t until Samsung demonstrated DDR on a mainboard that it was adopted commercially as system memory.
An original DDR RAM chip produced 8 data bits for every cycle of the clock, delivering 8 bits at a time to the I/O data pins. Original GDDR chips delivered 16 data bits for every clock cycle. This meant GDDR could move twice as much data per clock cycle.
DDR memory still uses a 64 bit wide bus. Since most of today’s DDR3 system memory is dual or triple channel, this means the overall bus width (or interface) for the system is 128 or 192 bit. Most graphics cards use between 4 and 8 channels, allowing for a memory interfaces up to 512 bit (64 bits per channel x 8 channels).
The large memory buses found in GDDR allow it to transfer large amounts of data on each clock cycle.
- Bus – A pathway for data between the memory chips and the memory controller
- Channels – Groups of memory chips. 2 or 3 in system. Usually 4-8 on graphics card
- Clock Speed – Cycles per second, measued in MHz. Every bus has a clock speed and a width
- Data Transfer Rate – Total bits per clock cycle on each pin/wire
- Latency – Clock cycles between data request and receipt
- Data Bus Width – Size of the memory bus, equal to total channels x bits of data per channel
- Interface – Same as data bus width